ああああ

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity kadai_11 is
port(
CLK,BCD1WR,BCD10WR,CIN : in std_logic;
CO : out std_logic;
DATAIN : in std_logic_vector( 3 downto 0);
BCD1 : out std_logic_vector( 3 downto 0);
BCD10 : out std_logic_vector( 2 downto 0));
end kadai_11;
architecture RTL of kadai_11 is
signal BCD1N : std_logic_vector(3 downto 0);
signal BCD10N : std_logic_vector(2 downto 0);
begin
BCD1 <= BCD1N;
BCD10 <= BCD10N;
process(CLK,BCD1WR) begin
if(BCD1WR = '1') then
BCD1N <= DATAIN;
elsif(CLK'event and CLK = '1') then
if(CIN = '1') then
if(BCD1N =9) then
BCD1N <= "0000";
else
BCD1N <= BCD1N + 1;
end if;
end if;
end if;
end process;
process(CLK,BCD10WR) begin
if(BCD10WR = '1')then
BCD10N <= DATAIN(2 downto 0);
elsif(CLK'event and CLK = '1')then
if(CIN = '1' and BCD1N=9) then
if(BCD10N=5) then
BCD10N <= "000";
else
BCD10N <= BCD10N + 1;
end if;
end if;
end if;
end process;
process(BCD10N,BCD1N,CIN) begin
if(CIN='1' and BCD1N=9 and BCD10N=5)then
CO <= '1';
else
CO <= '0';
end if;
end process;
end RTL;

あたい

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity kadai_11 is
port(
CLK,BCD1WR,BCD10WR,CIN : in std_logic;
CO : out std_logic;
DATAIN : in std_logic_vector( 3 downto 0);
BCD1 : out std_logic_vector( 3 downto 0);
BCD10 : out std_logic_vector( 2 downto 0));
end kadai_11;
architecture RTL of kadai_11 is
signal BCD1N : std_logic_vector(3 downto 0);
signal BCD10N : std_logic_vector(2 downto 0);
signal CLKN :integer;
begin
BCD1 <= BCD1N;
BCD10 <= BCD10N;
process(CLK,BCD1WR) begin
if(BCD1WR = '1') then
BCD1N <= DATAIN;
elsif(CLK'event and CLK = '1') then
CLKN <= CLKN + 1;
if(CIN = '1') then
if(CLKN mod 4 = 0 and BCD1N = 9) then
BCD1N <= "0000";
elsif(CLKN mod 4 = 0) then
BCD1N <= BCD1N + 1;
end if;
end if;
end if;
end process;
process(CLK,BCD10WR) begin
if(BCD10WR = '1')then
BCD10N <= DATAIN(2 downto 0);
elsif(CLK'event and CLK = '1')then
if(CIN = '1' and BCD1N=9 and CLKN mod 4 = 0) then
if(BCD10N=5) then
BCD10N <= "000";
else
BCD10N <= BCD10N + 1;
end if;
end if;
end if;
end process;
process(BCD10N,BCD1N,CIN) begin
if(CIN='1' and BCD1N=9 and BCD10N=5)then
CO <= '1';
else
CO <= '0';
end if;
end process;
end RTL;

あたいは

これ、何言語？

あげ